Tap ports to wire · drag blocks to arrange · scroll to zoom
CYCLE 000000
Virtual interposer
Route signals. Watch them change.
Values below come from the digital simulator. Change a crossbar's select input in the I/O desk; output routing updates at the next simulation step.
Physical pin acquisition and live register writes require compatible FPGA firmware and a registered hardware driver. Virtual values are never presented as measured pin voltages.
Verilog-2001
Inspect your design
GRAPH SYNCHRONIZED
Generated HDL follows the graph. Custom HDL is an independent, exportable draft; it is not parsed back into blocks or simulated by the graph engine.
Physical constraints
Give every port a home
Package pad numbers are not board header labels. No pin assignments are guessed. Verify the board schematic, supply pins, I/O voltage, and clock pin before hardware use.
Constraint preview
Human + agent, same actions
Structured input. Retrievable output.
Use window.USS.describe(), USS.getState(), and await USS.dispatch(action, input). Every response contains ok, status, and data or a recoverable error.
No embedded AI service or API key is required. Agents can use the JavaScript API or this labelled JSON console. Project imports are data only; hardware access requires an explicit browser device selection.
SIMULATION · PAUSED
Tap trace to place A / B cursors
Cycle-based functional simulation · no propagation-delay or physical timing model
Universal Silicon Studio digital-logic workbench
Offline-capable digital logic workbench for FPGA design. Simulate circuits, edit pin maps, and export Verilog, constraints, waveforms, and project files.
What it does
Builds unsigned digital circuits from connected logic blocks, simulates synchronous behavior cycle by cycle in a browser worker, displays signal traces, and exports Verilog, pin constraints, and project data. Sixteen starting presets include counters, interlocks, PWM, crossbars, adders, registers, LUTs, pulse and edge detectors, filters, and a memory scratchpad.
Who it is for and when to use it
For learners, educators, and hardware developers who want to sketch and test small synchronous logic designs locally before moving to a verified FPGA toolchain. It is suitable for digital-logic exploration and functional checks, not electrical or timing sign-off.
How to use it
Load a preset or start a blank circuit, then add blocks and connect output ports to input ports.
Set bus widths and virtual input values; use the properties panel to inspect or edit connections and slices.
Step or run the cycle-based simulator, change inputs in the I/O desk, and inspect waveform captures or triggers.
For an FPGA source package, choose a target and package, verify each physical pad against the board schematic, then export the Verilog, constraints, and project files.
Inputs
Block types, labels, widths from 1 to 16 bits, node positions, wire connections and bus slices, virtual input values, and parameters for counters, LUTs, pulse generators, filters, and other supported blocks. Project settings include an iCE40, ECP5, or custom target, package name, clock period, generated-versus-custom HDL mode, pin assignments and pull-ups, simulation cycles, waveform window and trigger. Optional hardware controls request a USB or serial device and its connection settings.
Outputs
Live simulation state and waveform traces; downloadable project JSON, graph-generated Verilog or the selected custom HDL draft, PCF or LPF pin constraints, VCD and CSV captures, trace JSON, build-source JSON, agent-schema JSON, and a schematic SVG. The build-source bundle contains source files, commands, and validation information; it does not contain synthesis results or a bitstream. Agent exports return structured content and can trigger a download only when requested.
Example use cases
Step through a counter or edge detector and inspect its cycle-by-cycle output.
Model a mux, arithmetic block, or simple interlock and validate the digital graph.
Export a Verilog design and pin-constraint draft for review in a separate FPGA toolchain.
Limitations and data
The simulator models unsigned, cycle-based logic only: it has no propagation-delay, analog, metastability, or physical-timing model; sequential blocks share one rising-edge clock and active-high synchronous reset. It does not parse custom HDL back into the graph or simulate a custom HDL draft. This file includes no synthesis/place-and-route binaries, device database, verified IP library, bitstream generator, or board-programming driver; real builds and flashing require trusted registered adapters. Resource use and maximum frequency remain unknown until an external toolchain runs. Verify package pin maps against the board documentation; package pads are not header labels. Safety/interlock examples are learning models, not certified controls. Projects autosave in this browser's localStorage when available; JSON imports are limited to 5 MiB, projects to 150 nodes and 600 wires, signals to 16 bits, and traces to 2,048 samples. The app has no remote project sync or embedded AI provider. The analytics tag may send page-view data to Google when online.
Agent interface
window.USS.describe() returns the manifest; getState() reads the project and simulator state; dispatch(action, input) supports validated project editing, imports, simulation, validation, exports, and history actions. generateVerilog() and generateConstraints() return source text. registerToolchain(adapter) and registerDriver(driver) accept trusted extension code; neither adapter is built in. Requests return structured success or recoverable errors, and successful updates publish the uss:statechange event. No AI service or API key is included.
Frequently asked questions
Does the app generate a ready-to-flash FPGA bitstream?
No. It exports build sources. A registered synthesis/route adapter and a compatible, verified programmer driver are required for bitstream generation and hardware programming.
Can it import and simulate arbitrary Verilog?
No. Custom HDL can be saved and exported as a draft, but the graph simulator does not parse or execute it.